To connect a semiconductor chip to a substrate in the related art, a wire bonding method using metal thin lines such as gold wires has been widely used. To meet requirements for e.g. higher functions, larger scale integration, and higher speed of semiconductor devices, a flip chip connection method (FC connection method) has been becoming popular, in which a conductive projection called a bump is formed on a semiconductor chip or a substrate to directly connect the semiconductor chip to the substrate.
A method for performing metal joining using solder, tin, gold, silver, copper and the like, a method for applying supersonic vibration to perform metal joining, and a method for causing the contraction force of a resin to hold mechanical contact, and the like, have been known as the flip chip connection method. From the viewpoint of the reliability of a connection portion, a method for performing metal joining using solder, tin, gold, silver, copper and the like is common.
Examples of the flip chip connection method also include a type of COB (Chip On Board) connection method frequently used in BGA (Ball Grid Array), CSP (Chip Size Package) and the like in order to provide connection between the semiconductor chip and the substrate. The flip chip connection method is also widely used in a type of COC (Chip On Chip) connection method in which bumps or wires are formed on semiconductor chips to connect the semiconductor chips (see Patent Literature 1, for example).
Packages for which there is great demand for further reductions in size and thickness or higher functions increasingly use chip-stack type package and POP (Package On Package) using the above-mentioned connection method laminated or multi-staged each other; TSV (Through-Silicon Via); and the like. These techniques are heavily used since three-dimensional arrangement can be performed rather than planar arrangement, which can attain a smaller package, are effective in an improvement in performance of semiconductors and reductions in noise, a mounting area and energy consumption, and receive attention as a semiconductor wiring technique of the next generation.